circuit note cn-0243 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more i nformation and/or support , visit www.analog.com/cn0243 . devices connected /referenced adrf6702 1200 mhz to 2400 mhz quadrature modulator with1550 mhz to 2150 mhz frac tional - n pll and integrated vco ad 9122 dual, 16 - bit, 1230 msps, txdac ? ad9516 -0 / ad9516 -1 / ad9516 -2 / ad9516 -3 / ad9516 -4 clock generator with integrated vco with various frequency range options from 1.45 ghz to 2.95 ghz high dynamic range rf transmitter signal chain u si ng single external frequency ref erence for dac sample clock and iq modulator lo generation rev.0 circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining it s suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. evaluation and desig n support circuit evaluation boards cn - 0243 circuit evaluation board (eval - cn0243 - eb1z ) design and integration files schematics, layout files, bill of materials circuit function and benefits t he combination of the adrf6702 iq m odulator and the ad9122 16- bit dual 1.2 gsps txda c has the dynamic range necessary for a modern high level qam or ofdm based wireless transmitter as shown in figure 1. the dynamic range external frequency reference input dual modulus pll with on chip vco external loop filter external loop filter ad9516 ad9122 adrf6702 pll reference input programmable divider programmable divider optional external 2 lo (i/o) internally generated 2 lo adrf6702 rf output ad9122 dac sample clock idac i channel passive interface filter qdac q channel passive interface filter 16-bit data bus (i) 16-bit data bus (q) 32-bit nco 2/4/8 interpolation filters 2/4/8 interpolation filters internal lo synthesizer/pll internal vco 10165-001 2 modulator core pll core (pfd, charge pump, divider) figure 1. ad9122, adrf6702 , and ad9516 used in a high dynamic range transmitter
cn-0243 circuit note rev. 0 | page 2 of 8 of th is circuit is good enough to enable both zif (zero if/ baseband) and cif (complex if up to 200 mhz to 300 mhz). the ad9122 has the option of up to 8 interpolation , as well as a 32 - bit nco for very fine if frequency selectivity. overall performance of a transmitter is highly dependent on the dynamic range of the components directly in the signal chain. in a mixed -signal transmitter using a dac and iq modulator, the noise floor and distortion characteristics of these components define the overall dynamic range of the signal chain. however, the noise floor of the dac can also be degraded by sample clock jitter, and the iq modulator performance is dependent on the noise and spur characteristics of its local oscill ator (lo). using high performance components for sample clock and lo generation is , therefore , key to a high performance transmitter. in addition, generating these signals physically close to the dac and modulator on the pcb and using a single external ref erence can make the design much simpler. generating the sample clock and lo (lo is very often a multi - ghz signal) separately and at some distance from the dac and iq modulator requires great care in the pcb layout. subtle layout errors can cause coupling t o and from these critical signals and degrade overall signal chain performance. the signal chain performance is also heavily dependent on the dac/ iq modulator interface filter. for optimal performance, this passive filter should be designed after careful analysis of the required system specifications. the adrf6702 includes an on - board fractional pll for lo generation so that a low frequency reference (typically less than 100 mhz) is all that is necessary to s ynthesize the iq modulator lo. using the pll in the ad9516 clock generator allows a single reference to generate both the dac sample clock and the pll reference for the adrf6702 . the circuit in figure 1 was built using the ad9516 -0 , but other members of the ad9516 family could be used depending on the desired internal vco frequency. circuit description adrf6702 iq modulator with internal lo synthesizer, synthesizer iq mod ulator interface the adrf6702 iq modulator is a unique device in several respects. in addition to its exceptional dynamic range, it also includes a fractional - n pll , which allows programming of discrete lo frequency steps of le ss than 25 khz while at the same time keeping the overall frequency multiplication small enough to avoid a large increase in phase noise from the reference to the synthesizer output. another aspect of the adrf6702 is the divide - by - 2 architecture of the iq modulator . traditional iq modulator s accept an lo input frequency at 1 the desired lo. internally, a distributed rc network creates the desired in - phase and quadrature lo signals f rom the single lo frequency input. because this is a passive rc network, the bandwidth over which quadrature m odulation accuracy is achieved is limited. also, for good quadrature accuracy, the external lo should be spectrally pure. harmonics on the lo with this traditional iq modulator architecture can degrade the overall modulation accuracy. for this reason, when using a pll synthesizer to generate an lo signal for a n iq modulator , a sharp band - pass or low - pass filter is often required at the iq modulator lo input. in the divide - by - 2 lo architecture of the adrf6702 , a simple digital divider is used internally to create nearly perfect quadrature over a wide band. the pll synthesizer generates the 2 lo internally, so that it does not have to be distributed around the pcb, and no filter is required between the synthesi zer and iq modulator lo because the 2 lo architecture is only sensitive to the edges of the lo signal, not the frequency content. for a detailed descripton of the effects of lo harmonics on a 1 iq modulator and the design of the lo filter, see circuit note cn - 0134. sampled signal to rf, overall spur floor a baseband signal goes through a number of steps on the way to the rf transmit frequency. the signal begins in the discrete 1065-002 ?4x ?245.76 ?184.32 ?122.88 ?61.44 61.44 122.88 184.32 245.76 dc frequenc y frequenc y (x-fd at a) 0db ?20db ?40db ?60db ?80db ?100db ?3x ?2x ?1x dc 1x 2x 3x 4x amplitude (dbfs) figure 2 . dac output spectrum, solid blue line represents baseband signal and images, dotted red line represents dac sinc function
circuit note cn-0243 rev. 0 | page 3 of 8 1065-003 ?4x ?245.76 ?184.32 ?122.88 ?61.44 61.44 122.88 184.32 245.76 dc frequenc y frequenc y (x-fd at a) 0db ?20db ?40db ?60db ?80db ?100db ?3x ?2x ?1x dc 1x 2x 3x 4x amplitude (dbfs) figure 3 . dac output spectrum using 4 interpolation , the thin blue line represents the dac interpola tion transfer function (sampled) domain and is synthesized by the dac into the analog domain. the results of this step are images and distortion products generated by the dac. as shown in figure 2, an ideal dac w ith no distortion will generate images of a baseband signal that must be filtered before being modulated. the use of interpolation filters such as those in the ad9122 can suppress most of the image energy, but an analog interface filter between dac and modulator will still be necessary. there is a trade - off, however, between the order of the dac interpolation and the order of the analog filter. higher dac interpolation rates mean lower required analog filter order and vice versa. figure 3 shows what the dac output spectrum looks like when using 4 interpolation, as an example. a multitude of spurious components a t rf the signal chain can add significant spurious component s to the spectrum, due b oth to modulation products, distortion produc ts, and integer multiples of the lo frequency. it we take into account all of the possibilities for spurious which we have discussed, the spurious content can consist of ( j lo_freq ) + ( k dac_sample_rate ) + ( l dac_nco_freq ) + ( m dac_input_if ) where j, k, l, and m are integer s over the range of negative infinity to positive infinity. dac/modulator passive interface filter the key to reducing the overall spurious spectrum is the ana log interface filter between the dac and the iq modulator . the design of the interface filter between the dac and iq modulator must take into account multiple aspects of performance : 1. filter topology, order , and 3 db cutoff frequency 2. at dc , the dac sees a l oad impedance equal to the dac termination resistors (typically a 100 ? differential impedance) in parallel with the input impedance of the iq modulator . the iq modulator impedance is often > 1k ? , so a shunt resistor is often used across the iq modulator inputs to create a similar load impedance to the source. unequal filter source and load impedances , as well as parasitics in the signal traces, may add unwanted ripple in the filter pass band. 3. pcb layout. as shown in figure 4 , the i and q baseband inputs on the adrf6702 iq modulator are located on opposite edges of the device. note the filter layout area within the dotted circles . to route the dac output signals to these pins, the traces must travel up and then back down to get to the baseband pins on th e adrf6702 . these differential signal traces should be of equal length, and any changes in direction of the trace should be done by using 45 bends. if these recommendations are not implemented , in - band rippl e, phase , or amplitude response may be degraded in the filter response. note that with this filter topology, the capacitors can be used differentially (across the signal path) or they can be used in a common - mode connection by placing the filter caps from the signal path pads to ground pads. there are conditions (discussed later in this circuit note ) where common - mode capacitors improve performance vs. diff erential - mode capacitors . 10165-004 figure 4 . pcb layout for transmitter, dac/mod in terface filter section
cn-0243 circuit note rev. 0 | page 4 of 8 4. to achieve optimal performance from the filter, these traces should be 100 ? differential, or 50 ? per line. note that with typical fr4 material, a 50 ? line results from a t/w ratio of 2:1. if higher impedance lines are desired it should be understood that the impedance of the line is a nonlinear function of t/w (t = board laye r thickness, w = width of trace). a thinner line results in a higher impedance line. with typical fr4 layer thicknesses, a 100 ? line can get very thin, often close to minimum design constraints. one solution to this is to void the ground layer underneath the trace and put another ground layer on the third layer of the pcb. this effectively doubles t and allows for a wider trace. dac_mod interface filter topology figure 5 shows a typical topology which gives a 5 th order maximally f lat butterworth response for a differential input and output impedance of 100 ?. . the actual response is given in figure 6 . this filter uses 4.6 pf capacitors at the source and load. this magnitude of capacitor value ( < 20 pf ) is typical of filters with high cutoff frequencies. p arasitics may have a significant effect on response when using these small capacitor values . l l1 l = 58.5nh r = 1p? port ip_bb num = 1 port in_bb num = 3 port ip_mod num = 2 port in_mod num = 4 c c1 c = 4.46893pf c c2 c = 14.461762pf c c3 c = 4.46893pf l l2 l = 58.5nh r = 1p? l l3 l = 58.5nh r = 1p? l l4 l = 58.51nh r = 1p? 1065-005 figure 5 . dac/mod interface filter topology, 5th order butterworth, 3 db bw = 220 mhz , 100 ? differential input and output impedance 0 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.2 0.4 0.6 0.8 1.0 s21 (db) frequency (ghz) 10165-006 s1 spc figure 6 . frequency response of filter topology given in figure 5 dac and distortion related spurious components the use of dac interpolation filters by themselves can reduce the spurious content at the modulator input and , therefore , the spurious content at rf. however, there may still be signif icant spurious content. figure 7 shows the rf output spectrum of the iq modulator under the following conditions; flo = 1940 mhz dac input data rate = 300 msps dac interpolation = 4 dac nco frequency = 150 mhz dac input if frequency = 8 mhz note that the strongest spurious component (aside from the fundamental at 2098 mhz) is the 2 component of the dac clock at 2400 mhz . this is likely a result of common and differ ential mode components of the dac output containing some spectrum from the dac clock. the common - mode rejection of the iq modulator input rejects much of this signal, but it is still contains significant energy. the next two highest spurs, at 2062 mhz and at 2242 mhz, also seem to be related to dac clock spurs. the spur at 2242 mhz is easily recognized as 2 (dac clock C dac fundamental) = 2400 ? 158. the spur at 2062 mhz is not so obvious, but looks like (3 lo ) ? ( 3 dac clock ) ? 158 = 5820 ? 3600 ? 15 8. if the analysis is correct, then we should be able to see significant spur reduction if we can suppress the common - mode component of the dac clock at the iq modulator inputs. 2098mhz 2400mhz 2242mhz 2062mhz 10165-007 figure 7. iq modulator rf output with dac/iq mod filter absent , lo = 1940 mhz , dac input if = 8 mh z, dac nco = 150 mhz, rf = 2098 mhz
circuit note cn-0243 rev. 0 | page 5 of 8 applying the differential butterworth filter gives significant spur level reduction, as shown in figure 8 . the strongest spurs are still at 206 2 mhz, 2242 mhz, and the 2 dac clock spur at 2400 mhz. all three spur ious components have been reduced significantly. 10165-008 2400mhz 2242mhz 2062mhz 2098mhz figure 8 . rf spectrum u sing 5th order butterworth filter, differential capacitors the common - mode rejection o f the dac/ iq modulator interface can often be improved by changing the topology of the interface filter. in figure 9 , the input and output 4. 7 pf caps are replaced by common - mode capacitors (9.0 pf ) from both sides of the filter i nput and both sides of the filter output to ground . this does not change the overall differential filter mode response but does have an effect on this board on the overall spurious content at rf. the harmonics mentioned earlier at 10165-009 2400 mhz 2242 mhz 2062 mhz 2098 mhz figure 9. rf spectrum using 5th order butterworth filter, combination of differential and common - mode capacitors used in the dac_mod filter 2062 mhz and 2242 mhz are down a few db more, and there has been about a 15 db reduction in the 2 dac clock co mponent, nearly to the noise floor. the topology and results shown here may vary from layout to layout, so it is always to the advantage of the designer to experiment with the layout of the filter, specifically which mix of differential and common - mode c apacitors results in the lowest overall spur floor. synthesizer path and pll phase noise as shown in figure 1 , t h is circuit uses a single external reference to generate the ad9122 dac sample clock and the reference clock for the pll in the adrf6702 . the ad9516 is fundamental in providing the flexibility to do this. the ad9516 contains a pll and integrated vco. it also contains a number of outputs that can be programmed for differential lvpecl, lvds , or single- ended cmos , with independent divider settings for each output path . in this circuit, one of these output paths is used for the dac clock and another output is used for the reference input of the f ractional -n pll in the adrf6702 . the advantage of using a fractional pll in the adrf 6702 is twofold. first, the fractional pll allows very fine tuning of the output lo. as an example, with an input frequency of 38.4 mhz and a programmed mod value in the adrf 6702 of 1536, the lo can be programmed in increments of 25 khz. the second advantage is that the reference frequency does not have to be equal to lo freq/divider ratio, but can be much higher, leading to a lower divider ratio. because the output phase noise is a function of the reference phase noise multiplied by the divider ratio, this means inherently lower phase noise at rf. one of the key metrics in a synthesizer system is the amount of phase noise added by the individual pll and dividers. figure 10 shows the noise floor of the spectrum analyzer doing the measurement (green trace), the phase noise of the reference generator (red) , and the phase noise of an output tone at an rf frequency of 1961 mhz with an lo of 1940 mhz (yellow). t he combination of the pll in the ad9516 and the adrf6702 does generate noticeably high close - in phase noise (less than 500 khz offset from carrier) b ut does not c ontribute significant wideband noise to the system. the loop filters for the vcos in both the ad9516 and adrf6702 are set to bandwidth s of ~100 khz in the measur e ment circuit. close - in phase noise may be reduced by lowering the bandwidth of these loop filters. system specifications should be reviewed to determine how much close - in phase noise can be tolerated for a given s ystem.
cn-0243 circuit note rev. 0 | page 6 of 8 10165-010 spectrum analyzer reference generator 1961mhz rf output (lo = 1940mhz) figure 10 . spectrum analyzer noise floor, r e ference phase noise, and rf output phase noise common variations as described in the last section, pll performance can be adjusted by varying the bandwidth of the loop filters. there is a trade - off between loop filter ba ndwidth and frequency settling time that must be taken into account. if a dac such as the ad9122 is used, the dac nco can also be used for fine frequency hopping, al though there is a limit to the hopping speed since the nco requires programming via a n spi port. newer clock synthesis and distribution devices such as the ad9520 and ad 9523 may provide improvements in phase n oise. circuit evaluation a nd test the e va l - cn0243 - eb1z evaluation board requires the following equipment and software for signal generation and basic measurement : equipment needed ? 5 v power s upply ? low phase noise reference s ource (10 mhz to 200 mhz range @ +3 dbm) , rohde & schwarz sma100, low noise o ption , or equivalent ? dpg2 digital pattern generator from analog devices ? high dynamic range spectrum a nalyzer , a gilent e4440a or equivalent ? analog devices e va l - adf4xxxz usb adapt er software ? dpg2 software (included with dpg) ? adrf6702 s oftware available at www.analog.com/adrf6702 10165-011 figure 11 . eval - cn0243 - eb1z evaluation board 10165-012 figure 12 . bench test se tup setup and test the following steps are required to properly run the e va l - cn0243 - eb1z evaluation board: 1. before powering up, connect all instruments, usb adapters, and cables , as shown in figure 13. 2. there is only a single 5 v power supply required. this should be connected to the female banana plugs on the e va l - cn0243 - eb1z board. make sure this supply is connected, then turn on the +5 v supply. the total current at this point should be 850 ma to 900 ma. 3. the dpg2 software c ontains a gui to program the ad9122 . program the ad9122 for the correct interpolations rate and nco (if desired). 4. turn on the dpg2 software itself. if all cables an d software are working correctly, the software should recognize the dac input data rate and display it in the lower right hand corner of the dpg gui. note that this
circuit note cn-0243 rev. 0 | page 7 of 8 pc i q usb +5v gnd usb 1065-013 usb adapter board dpg2 digital pattern generator eval-cn0243-eb1z evaluation board reference frequency generator 10mhz ? 200mhz +3dbm spectrum analyzer power supply pll reference input rf output iq d at a digital interface figure 13. test setup functional block diagram data rate should be equal to the dac sample rate (614.4 msps) in figure 13 divid ed by the programmed interpolation rate of the ad9122 . 5. note that as the various devices are activated and programmed, the current will incre ase. at the end of this exercise, the current should be between 1 .4 a and 1.5 a, depending on dac sample rate. 6. use the dpg2 software to create a waveform (single, multi tone, or comms standard signals are available). a digital back - off of ?8 db should be used initially to optimize linearity of the dac/ adrf6702 combination. complex signal generation should also be selected in the dpg2 gui. when the waveform is created, use the " load " and " play " buttons in the gui to load the digital pattern into the dpg memory itself. 7. start the adrf6702 gui. to begin with, the only options in the adrf6702 gui which need to be selected are the input reference frequency and lo output frequency. to program these values, click the reference input frequency or the lo output values in the top center of the adrf6702 gui. another window will app ear which will allow you to enter these values. important : a fter entering these values, the user must finish with a carriage return to make sure that the values are entered into the gui. 8. programming the adrf67 02 is the last step in setting up the e va l - cn0243 - eb1z eval uation board. as an example , if the dpg2 generates a series of tones (20 mhz to 25 mh z with 1 mh z spacing) @ ?8 db back - off , and the lo of t he adrf6702 is programmed to 1940 mhz, the spectrum should look very similar to that shown in figure 14. ?20 ?30 ?40 ?50 ?60 ?120 ?110 ?100 ?90 ?80 ?70 center 1.94ghz 10mhz/div span 100mhz 10165-014 ref ?20dbm a tt 10dbm rbw 10khz vbw 30khz swt 15ms marker 1 [t1] ?104.90db 1.89005ghz figure 14 . spectrum of complex multitone signal at lo frequency of 1940 mhz at adrf6702 rf output , desired sideband offset: +20 mhz, undesired si deband offset: ?20 mhz
cn-0243 circuit note rev. 0 | page 8 of 8 l earn more cn - 0243 design support package: www.analog.com/cn0243- designsupport dpg2 digital pattern generator: www.analog.com/dpg_dac_eval_platfform adisimpll design tool adisimrf design tool data sheets and evaluation boards adrf6702 data s heet adrf6702 evaluation board ad9122 data s heet ad9122 evaluation board ad9516 - 0 data s heet ad951 6-0 evaluation board ad9516 -1 data sheet ad9516 -1 evaluation board ad9516 -2 data sheet ad9516 - 2 evaluation board ad9516 -3 data sheet ad9516 - 3 evaluation board ad9516 -4 data sheet ad9516 - 4 e valuation board revision history 10/ 11 revision 0: initial version (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual property of analog devices or its licensors. wh ile you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectua l property by application or use of the circuits from the lab circuits . informat ion furnished by analog devices is believed to be accurate and reliable. however, "circuits from the lab" are supplied "as is " and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of mer chan tability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. analog devices reserves th e right to change any circuits from the lab circuits at any time without notice but is under no obligation to do so. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn10165 -0- 10/11(0)
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